The Chipit Iridium Edition offers ASIC and SoC design engineers unprecedented speed and flexibility to verify and debug their designs.

Set for launch at DAC 2006 in San Francisco (24th to 28th July), the Chipit Iridium Edition is billed as giving ASIC and SoC design engineers unprecedented speed and flexibility to verify and debug their designs. This very cost-effective solution for all stages of hardware-assisted verification shortens the time to market by eliminating costly respins and by providing an early prototype for the software development. 'With the Iridium Edition, we created a very handy prototyping system for ASIC and IP designers of medium design sizes that provides extensive design debugging capabilities and an easy to use verification system'.

'It combines our patented technologies and other proven functionalities from its 'big brother', the successful Chipit Platinum Edition for multi-million-ASIC-gate designs', said Heiko Mauersberger, CTO of ProDesign.

The highlight of the new system is its maximum of flexibility.

It can be scaled from one up to six FPGAs Xilinx Virtex-4 FPGAs (XC4VLX100/160/200) and handles ASIC design capacities from 1 to 6 million ASIC gates.

ProDesign's patented 3D switching technology offers highest interconnection flexibility between all FPGAs and allows to adjust the connection architecture to the design in the best way, to achieve a maximum system speed performance up to 200MHz.

Furthermore, designers can use up to 2580 free user I/Os on eight different extension board sites to connect for example to standard ProDesign extension boards like external memories, Ethernet interface, PCI-Express interface or customer specific extension boards to test their designs in a real-world environment.

Other features of the system are embedded on board SSRAM memory and on board DDR- and DDR2-SDRAM memory sockets.

Chipit Iridium Edition is a stand-alone system that communicates with the host via ProDesign's proprietary 528Mbit UMRBus communication system technology, allowing for multiple independent communication channels between host and design to be set up for interaction with the ASIC design.

Users can choose between a C/C++ and a Tcl/Tk programming interface and have the option to store and load the configuration data via Ethernet or with an integrated SD card interface.

'Our worldwide customer base asked for an ASIC prototyping system for small to medium ASIC design sizes with more performance, flexibility and debugging capabilities'.

'Chipit Iridium Edition combines the features of Chipit Platinum with a completely new system architecture at a very attractive price'.

'This extends our product family, and we are now able to serve a greater range of customers requiring high-end ASIC prototyping', added Gunnar Scholl, ProDesign's Director of Marketing and Business Development.

Chipit Iridium Edition comes with a comprehensive software package including Chipit Manager, Switch Routing Tool, Visibility Tool, HDL Bridge and Signal Tracker, Host Controlled Debug Tool, and an SCE-MI interface for transactional based verification.

The Chipit Manager for complete project administration and system configuration supports design implementation (synthesis/place and route) and handles design partitioning on the prototyping system.

The Visibility Tool eases debugging of the design by executing the internal design signals after synthesis/place and route which can then be analysed for example with tools such as logic analysers.

Other highlights for debugging are HDL Bridge and Signal Tracker.

HDL Bridge is a powerful tool that provides a direct link between a simulation environment (RTL or gate level) to part or the whole DUT (design under test) that is loaded in the Chipit system.

This ensures that the entire design or parts of it run in hardware already in the simulation phase.

Combined with Signal Tracker for visualisation of the internal signals in the simulator, the designer is provided with an ideal solution for rapid design debugging.

The host-controlled debugging tool allows the user access to all design registers without any synthesis and place and route.

The signal values will be stored using VCD files and can be visualised in a wave form viewer.